Samsung S5PC110 Manual page 1899

S5PC110_UM
PCM_CTL
TX_MSB
_POS
RX_MSB
_POS
PCM_TXFIFO
_EN
PCM_RXFIFO
_EN
PCM_PCM
_ENABLE
Bit
[4] Controls the position of the MSB bit in the serial output stream
relative to the PCMSYNC signal
0 = MSB sent during the same clock that PCMSYNC is high
1 = MSB sent on the next PCMSCLK cycle after PCMSYNC is
high
[3] Controls the position of the MSB bit in the serial input stream
relative to the PCMSYNC signal
0 = MSB is captured on the falling edge of PCMSCLK during the
same cycle that PCMSYNC is high
1 = MSB is captured on the falling edge of PCMSCLK during the
cycle after the PCMSYNC is high
[2] Enables the TXFIFO
When the enable is LOW the internal FIFOs will clear and
reinitialize
[1] Enables the RXFIFO
When the enable is LOW the internal FIFOs will clear and
reinitialize
[0] PCM enable signal. Enables the serial shift state machines.
The enable must be set HIGH for the PCM to operate.
When the enable is LOW, the PCM outputs will not toggle
(PCMSCLK, PCMSYNC, and PCMSOUT). Additionally when the
enable is LOW, the internal divider-counters are held in reset.
Description
5 PCM AUDIO INTERFACE
Initial State
0
0
0
0
0
5-8