Samsung S5PC110 Manual page 1390

S5PC110_UM
5.1.5.14 Pixel Processing
The Pixel Processing pipeline takes the result of vertex processing process from the memory and performs a
number of processes to generate the final rasterized pixels. This can be divided into three main stages:
•
Hidden Surface Removal (ISP)
•
Texturing and Shading (TSP, Iterators, TAG, TF, and USSE)
•
Pixel Formatting (Pixel Co-Processor)
5.1.5.15 Image Synthesis Processor
To determine the visible pixels for each triangle in a given tile before being textured and shaded, the Image
Synthesis Processor (ISP) specifies the first stage of pixel-processing pipeline that performs hidden surface
removal. This is a key feature of the PowerVR architecture that is referred to as deferred texturing and shading. It
performs a pixel accurate occlusion detection operation ahead of the computationally intensive pixel shading
operations.
5.1.5.16 TSP
The TSP parameter fetches requests, and parses position and TSP vertex data from internal 3D display list--for
visible primitives produced by the hidden surface removal engine (ISP).
To set up triangle for the TSP, the TSP FPU uses vertex data sourced from the TSP parameter fetch. Multiple
plane equations are produced that define how colors and texture coordinate sets are interpolated across
primitives.
5.1.5.17 Texture Address Generator
The Texture Address Generator (TAG) receives a set of coordinates from iterators or the USSE, along with their
corresponding state information. From this, it calculates a set of addresses to perform the required texture lookup.
It also generates a set of coefficients to be used by the return Texture Filter (TF) module.
5.1.5.18 Texture Filter
The Texture Filter (TF) receives data from the cache, following requests submitted by the TAG module, and filters
the resultant data as required. It computes bilinear, trilinear, and anisotropic filtering results. These results are
then passed into the USSE for combining with the complex pixel shader calculated colors that are written to the
Pixel Co-processor module.
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