Samsung S5PC110 Manual page 1522

S5PC110_UM
7.12.1.130 SDO Interrupt Request Register (SDO_IRQ, R/W, Address = 0xF900_0280)
SDO_IRQ
Reserved
Vsync Interrupt Request
7.12.1.131 SDO Interrupt Request Masking Register (SDO_IRQMASK, R/W, Address = 0xF900_0284)
SDO_IRQMASK
Reserved
Vsync Interrupt Request
Masking
7.12.1.132 SDO Closed Caption Data Registers (SDO_ARMCC, R/W, Address = 0xF900_03C0)
SDO_ARMCC
Reserved
Display Control Character
of Closed Caption Data
Non Display Control
Character of Closed
Caption Data
NOTE: This register is used for European Caption as well as US Closed Caption.
Bit
[31:1] Reserved, read as zero, do not modify
[0] 0 = No interrupt
1 Interrupt request pending
(This interrupt is requested if TVOUT module generates
the falling edge of vertical synchronization pulses at each
field. Write 1 to reset this bit.( Writing '0' has no effect ).
Bit
[31:1] Reserved, read as zero, do not modify
[0] 0 = Enables Interrupt request
1 = Disables Interrupt request
(The status pending bit of SDO Interrupt Request
Register is asserted even if the request is disabled. Only
the request to MCU will be disabled. )
Bit
[31:16] Reserved, read as zero, do not modify
[15:8] Bit alignment of the Display Control Character register is
in their incoming order. The first incoming bit becomes
LSB, i.e. Display Control Character [7:0] = {p, b6, b5, b4,
b3, b2, b1, b0}, where bn represents data bit with their
incoming order n, and p denotes their odd parity bit.
[7:0] Bit alignment of the Non Display Control Character
register is in their incoming order. The first incoming bit
becomes LSB, i.e. Non Display Control Character [7:0] =
{p, b6, b5, b4, b3, b2, b1, b0}, where bn represents data
bit with their incoming order n, and p denotes their odd
parity bit.
Description
Description
Description
7 6BTVOUT & VIDEO DAC
Initial State
0
0
Initial State
0
0
Initial State
0
0
0
7-50