Samsung S5PC110 Manual page 1971

Risc microprocessor
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S5PC110_UM
2.3.1.1 Feed Control (FCINTSTAT, R, Address = 0xEA00_0000)
FCINTSTAT
Reserved
BRDMAINT
BTDMAINT
HRDMAINT
PKDMAINT
2.3.1.2 Feed Control (FCINTENSET, R/W, Address = 0xEA00_0004)
FCINTENSET
Reserved
BRDMAINTENSET
BTDMAINTENSET
HRDMAINTENSET
PKDMAINTENSET
2.3.1.3 Feed Control (FCINTENCLR, R/W, Address = 0xEA00_0008)
FCINTENCLR
Reserved
BRDMAINTENCLR
BTDMAINTENCLR
HRDMAINTENCLR
PKDMAINTENCLR
Bit
[31:4]
Reserved
[3]
Specifies the interrupt signal of block cipher receiving
DMA.
[2]
Specifies the interrupt signal of block cipher transmitting
DMA.
[1]
Specifies the interrupt signal of hash receiving DMA.
[0]
Specifies the interrupt signal of PKA DMA.
Bit
[31:4]
Reserved
[3]
Specifies the interrupt enable set signal of block cipher
receiving DMA.
[2]
Specifies the interrupt enable set signal of block cipher
transmitting DMA.
[1]
Specifies the interrupt enable set signal of hash
receiving DMA.
[0]
Specifies the interrupt enable signal of PKA DMA.
Bit
[31:4]
Reserved
[3]
Specifies the interrupt enable clear signal of block cipher
receiving DMA.
[2]
Specifies the interrupt enable clear signal of block cipher
transmitting DMA.
[1]
Specifies the interrupt enable clear signal of hash
receiving DMA.
[0]
Specifies the interrupt enable clear signal of PKA DMA.
Description
Description
Description
2 ADVANCED CRYPTO ENGINE
R/W
Initial State
0
0
0
0
0
R/W
Initial State
0
0
0
0
0
R/W
Initial State
0
0
0
0
0
2-16

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