Samsung S5PC110 Manual page 1976

S5PC110_UM
2.3.1.15 Feed Control (FCHRDMAC, R/W, Address = 0xEA00_0048)
FCHRDMAC
Reserved
BYTESWAP
FLUSH
2.3.1.16 Feed Control (FCPKDMAS, R/W, Address = 0xEA00_0050)
FCPKDMAS
STARTADDR
2.3.1.17 Feed Control (FCPKDMAL, R/W, Address = 0xEA00_0054)
FCPKDMAL
LENGTH
Bit
[31:2] Reserved
[1] If this bit is high, then the data read from the bus is
byte-swapped in a word boundary. If this bit is low
(default), then the data is handed over to the FIFO
without byte-swap. For little endian bus, this bit should
be '1'.
[0] If this bit is high, then data flushes out from FIFO and
DMA. After flushing, the start address keeps the
stopped address, and the length is 0. The flushing state
should be released by writing value '0' to this bit.
Bit
[31:0] Specifies the Start Address of DMA. The address needs
to be aligned by 32-bit. Its value increases by 4 after
every transaction.
Bit
[31:0] Specifies the Block length of DMA. The length needs to
be aligned by 32-bit. Its value decreases by 4 after
every transaction.
Description
Description
Description
2 ADVANCED CRYPTO ENGINE
R/W Initial State
0
0
0
R/W Initial State
0
R/W Initial State
0
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