Samsung S5PC110 Manual page 1832

S5PC110_UM
The Data is aligned in the TX FIFO for 24-bit/channel BLC as shown in
31
INVALID
INVALID
INVALID
INVALID
Once the data is written to the TX FIFO the TX channel can be made active by enabling the I2SACTIVE bit in the
I2SCON Register (IIS Control Register).
The data is then serially shifted out with respect to the bit clock SCLK and word select clock LRCLK.
The TXCHPAUSE in the I2SCON Register (IIS Control Register) can stop the serial data transmission on the
I2SSDO.The transmission is stopped once the current Left/Right channel is transmitted.
If the control registers in the I2SCON Register (IIS Control Register) and I2SMOD Register (IIS Mode
Register) are to be reprogrammed then it is advisable to disable the TX channel.
If the TX channel is enabled while the FIFO is empty, no samples are read from the FIFO.
The Status of TX FIFO can be checked by checking the bits in the I2SFIC Register (IIS FIFO Control
Register).
BLC = 10 (24-bit/channel)
23
Figure 2-8 TX FIF0 Structure for BLC = 10 (24-bit/channel)
Figure 2-8.
Left Channel
Right Channel
Left Channel
Right Channel
2 IIS MULTI AUDIO INTERFACE
0
LOC 0
LOC 1
LOC 2
LOC 3
LOC 4
LOC 5
LOC 6
LOC 7
LOC 8
LOC 9
LOC 10
LOC 11
LOC 12
LOC 13
LOC 14
LOC 15
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