Samsung S5PC110 Manual page 1871

Risc microprocessor
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S5PC110_UM
3.7.1.3 IIS-BUS Interface Special Registers (IISFIC)
IISFIC, R/W, Address = 0xE210_0008
IISFIC, R/W, Address = 0xE2A0_0008
IISFIC
Reserved
[31:16]
TFLUSH
FTXCNT
RFLUSH
FRXCNT
3.7.1.4 IIS-BUS Interface Special Registers (IISPSR)
IISPSR, R/W, Address = 0xE210_000C
IISPSR, R/W, Address = 0xE2A0_000C
IISPSR
Reserved
[31:16]
PSRAEN
Reserved
PSVALA
Reserved
Bit
Reserved. Program to zero.
[15]
TX FIFO flush command.
0 = No flush
1 = Flush
[14:8]
TX FIFO data count. FIFO has 64 dept, so value ranges
from 0 to 64.
N: Data count N of FIFO
[7]
RX FIFO flush command.
0 = No flush
1 = Flush
[6:0]
RX FIFO data count. FIFO has 64 dept, so value ranges
from 0 to 64.
N: Data count N of FIFO
Bit
Reserved. Program to zero.
[15]
Pre-scaler (Clock divider) A active.
0 = Inactive
1 = Active
[14]
Reserved. Program to zero.
[13:8]
Pre-scaler (Clock divider) A division value.
N: Division factor is N+1
[7:0]
Reserved. Program to zero.
Description
Description
3 IIS-BUS INTERFACE
R/W
Initial State
R/W
16'b0
R/W
1'b0
R
7'b0
R/W
1'b0
R
7'b0
R/W
Initial State
R/W
16'b0
R/W
1'b0
R/W
1'b0
R/W
6'b0
R/W
8'b0
3-20

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