Samsung S5PC110 Manual page 1646

S5PC110_UM
10.3.3.4 Control Registers (STATUS, S/W, Address = 0xFA11_0010)
STATUS
Authen_Ack
Aud_Fifo_Ovf
Update_Ri_Int
-
An_Write_Int
Watchdog_Int
I2c_Init_Int
Bit
[7] When HDCP is authenticated, this read-only bit occurs. It
keeps the authentication signal without interruption. It is not
cleared at all.
This bit specifies just one delayed signal of authen_ack from
HDCP block. It is not an interrupt source.
0 = Not authenticated
1 = Authenticated
[6] If audio FIFO overflows, this bit is set. Once set, it should be
cleared by the host.
0 = Not full
1 = Full
[5] Reserved
[4] Specifies the Ri interrupt status bit. If it is written by 1, it is
cleared.
0 = Interrupt does not occur
1 = Interrupt occurs
[3] Reserved
[2] Indicates that {An} random value is ready. If it is written by 1,
it is cleared.
0 = Interrupt does not occur
1 = Interrupt occurs
[1] Indicates that the 2nd part of HDCP authentication protocol is
initiated, and CPU should set a watchdog timer to check 5
seconds interval.
If it is written by 1, it is cleared.
0 = Interrupt does not occur
1 = Interrupt occurs
[0] Indicates that the 1st part of HDCP authentication protocol
can start.
If it is written by 1, it is cleared.
0 = Interrupt does not occur
1 = Interrupt occurs
10 9BHIGH-DEFINITION MULTIMEDIA INTERFACE
Description Initial State
0
0
0
0
0
0
0
0
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