Samsung S5PC110 Manual page 1404

S5PC110_UM
Register
MFC_COMMON_SI_RG_
3
MFC_COMMON_SI_RG_
4
MFC_COMMON_SI_RG_
5
MFC_COMMON_SI_RG_
6
MFC_COMMON_SI_RG_
7
MFC_COMMON_SI_RG_
8
MFC_COMMON_SI_RG_
9
MFC_COMMON_SI_RG_
10
MFC_COMMON_SI_RG_
11
MFC_COMMON_CHx_R
G_1
MFC_COMMON_CHx_R
G_2
MFC_COMMON_CHx_R
G_3
MFC_COMMON_CHx_R
G_4
MFC_COMMON_CHx_R
G_5
MFC_COMMON_CHx_R
G_6
MFC_COMMON_CHx_R
G_7
MFC_COMMON_CHx_R
G_8
Address R/W
0xF170_200C R
0xF170_2010 R
0xF170_2014 R
0xF170_2018 R
0xF170_201C R
0xF170_2020 R
0xF170_2024 R
0xF170_2028 R
0xF170_202C R
0xF170_2044 R/W Start address of the CPB (coded picture
or
0xF170_2084
0xF170_2048 R/W Decoding unit size register
or
0xF170_2088
0xF170_204C R/W Channel descriptor buffer address
or
0xF170_208C
0xF170_2050 W
or
0xF170_2090
0xF170_2054 W
or
0xF170_2094
0xF170_2058 R/W CPB size register
or
0xF170_ 2098
0xF170_205C R/W Descriptor buffer size register
or
0xF170_209C
0xF170_2060 R/W Release buffer register to specify the
or
0xF170_20A0
Description
Required buffer number register
Luminance address register for display
Chrominance address register for display
Decoded frame size for a frame
Display status register
Frame type register
Luminance address register in decoding
order
Chrominance address setting register in
decoding order
Decoding status register
buffer) in the external stream buffer.
Vertical resolution register for DivX 3.11
Horizontal resolution register for DivX 3.11
individual DPB availability
6 5BMULTI FORMAT CODEC
Reset Value
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
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