Table of Contents
Advertisement
S5PC110_UM
5.6.1.7 PCM FIFO Status Register (PCM_FIFO_STAT)
The PCM_FIFO_STAT register is used to report FIFO status.
•
PCM_FIFO_STAT, R, Address = 0xE230_0018
•
PCM_FIFO_STAT, R, Address = 0xE120_0018
•
PCM_FIFO_STAT, R, Address = 0xE2B0_0018
The bit definitions for the PCM_IRQ_STATUS Register are described below:
PCM_FIFO_STAT
Reserved
TXFIFO_COUNT
TXFIFO_EMPTY
TXFIFO_ALMOST_EMPTY
TXFIFO_FULL
TXFIFO_ALMOST_FULL
RXFIFO_COUNT
RXFIFO_EMPTY
RXFIFO_ALMOST_EMPTY
RX_FIFO_FULL
RX_FIFO_ALMOST_FULL
5.6.1.8 PCM Interrupt Clear Register (PCM_CLRINT)
The PCM_CLRINT register is used to clear the interrupt. Interrupt service routine is responsible for clearing
interrupt asserted. Writing any values on this register clears interrupts for both ARM and DSP. Reading this
register is not allowed. Clearing interrupt must be prior to resolving the interrupt condition; else, another interrupt
that would occur after this interrupt may be ignored.
•
PCM_CLRINT, W, Address = 0xE230_0020
•
PCM_CLRINT, W, Address = 0xE120_0020
•
PCM_CLRINT, W, Address = 0xE2B0_0020
Bit
[31:20]
Reserved
[19:14]
TXFIFO data count (0~32).
[13]
To indicate whether TXFIFO is empty.
[12]
To indicate whether TXFIFO is almost empty.
[11]
To indicate whether TXFIFO is full.
[10]
To indicate whether TXFIFO is almost full.
[9:4]
RXFIFO data count (0~32).
[3]
To indicate whether RXFIFO is empty.
[2]
To indicate whether RXFIFO is almost empty.
[1]
To indicate whether RXFIFO is full.
[0]
To indicate whether RXFIFO is almost full.
Description
5 PCM AUDIO INTERFACE
Initial State
0
0
0
0
0
0
0
0
0
0
0
5-15
- Quick Links:
- Architectural Overview
Hide quick links:
Advertisement
Chapters
Table of Contents
