Samsung S5PC110 Manual page 1685

S5PC110_UM
10.3.4.2 SPDIF Registers (SPDIFIN_OP_CTRL, R/W, Address = 0xFA13_0004)
SPDIFIN_OP_CTRL
-
op_ctrl
Bit
[7:2] Reserved
[1:0] 00b = Specifies the software reset
01b = Specifies the status checking mode (run)
11b = Specifies the status checking and HDMI operation
modes (run with HDMI)
Others = Undefined, do not use
00b = During a software reset, all state machines are set
to the idle or init state and all internal registers are set to
their initial values. Interrupt status registers are cleared,
all other registers that are writable by the system
processor keep their values.
01b = This command should be asserted after
SPDIFIN_CLK_CTRL.power_on is set. SPDIFIN starts
the clock recovery. When recovery is done, SPDIFIN
detects preambles of SPDIF signal format and stream
data header, abnormal time signal input, abnormal signal
input, and also reports these status via interrupts in
SPDIFIN_IRQ_STATUS.
11b = Specifies the "01b" case operations, checks
internal buffer overflow, and writes received data, which
can be either audio sample word of PCM or payload of
stream. Data will be transferred via HDMI.
- Assert 'op_ctrl'=11b after SPDIFIN_IRQ_STATUS.
ch_status_recovered_ir is asserted at least once for linear
PCM data.
- Assert 'op_ctrl'=11b after SPDIFIN_IRQ_STATUS.
stream_header_detected_ir is asserted at least once for
non-linear PCM stream data.
10 9BHIGH-DEFINITION MULTIMEDIA INTERFACE
Description Initial State
6b000000
0
10-76