Samsung S5PC110 Manual page 1842

S5PC110_UM
IISMOD
BLC [14:13]
CDCLKCON
MSS
RCLKSRC
TXR
LRP
SDF
RFS
Bit
Bit Length Control Bit Which decides transmission of
8/16/24 bits per audio channel for final mixed sound Tx
output or Rx input.
00 = 16 Bits per channel
01 = 8 Bits Per Channel
10 = 24 Bits Per Channel
11 = Reserved
[12] Determine direction of codec clock source (I2S_CDCLK)
0 = Supply RCLK to I2S_CDCLK (external codec chip)
1 = Get clock (to CLKAUDIO) from I2S_CDCLK (external
codec chip)
(Refer to
Figure
[11] Master or slave mode select
0 = Master mode
1 = Slave mode
[10] Select RCLK clock source
0 = Using Audio bus clock
1 = Using I2SCLK
(Refer to
Figure
[9:8] Transmit or receive mode select.
00 = Transmit only mode
01 = Receive only mode
10 = Transmit and receive simultaneous mode
11 = Reserved
[7] Left/Right channel clock polarity select.
0 = Low for left channel and high for right channel
1 = High for left channel and low for right channel
[6:5] Serial data format.
00 = IIS format
01 = MSB-justified (left-justified) format
10 = LSB-justified (right-justified) format
11 = Reserved
[4:3] IIS root clock (codec clock) frequency select.
00 = 256 fs, where fs is sampling frequency
01 = 512 fs
10 = 384 fs
11 = 768 fs
Note: Even in the slave mode, this bit should be set for
correct operation.
Description
2-3)
2-3)
2 IIS MULTI AUDIO INTERFACE
R/W Initial State
R/W 00
R/W 0
R/W 0
R/W 0
R/W 00
R/W 0
R/W 00
R/W 00
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