Samsung S5PC110 Manual page 1648

S5PC110_UM
10.3.3.7 Control Registers (HPD, R/W, Address = 0xFA11_0030)
HPD
-
Sw_Hpd
Hpd_Sel
NOTE: If ENC_EN (0xFA11_0044) is disabled (not using HDCP), HPD must be controlled by S/W. If you don't use S/W
control, it is possible that HDMI core works abnormally.
10.3.3.8 Control Registers (MODE_SEL, R/W, Address = 0xFA11_0040)
MODE_SEL
-
Hdmi_Mode
Dvi_Mode
* DVI mode gets a higher priority than HDMI.
10.3.3.9 Control Registers (ENC_EN, R/W, Address = 0xFA11_0044)
ENC_EN
-
Hdcp_Enc_En
Bit
[7:2] Reserved
[1] If HPD_SEL bit is set, this SW_HPD signal is used for HPD
(HDMI/ DVI cable plugging). However, if this bit is set to low
during HDMI transmission, status machines in HDCP core are
reset. Note that other HDCP register values are not
influenced.
0 = Low (unplugged)
1 = High (plugged)
[0] It this bit is cleared, the I_HPD signal from the I/O port is used
for HPD. If set, the SW_HPD signal is used for HPD.
0 = HPD signal
1 = SW_HPD internal HPD signal
Bit
[7:2] Reserved
[1] Selects a mode.
0 = Disables
1 = Enables
[0] Selects a mode.
0 = Disables
1 = Enables
Bit
[7:1] Reserved
[0] If this bit is set, the HDCP encryption is applied. Before setting
this bit, the HDCP authentication process has to be completed.
0 = Encryption disables
1 = Encryption enables
10 9BHIGH-DEFINITION MULTIMEDIA INTERFACE
Description
Description
Description
Initial State
6b000000
0
0
Initial State
6b000000
0
0
Initial State
7b0000000
0
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