Samsung S5PC110 Manual page 1839

S5PC110_UM
IISCON
FTXURSTATUS
FTXURINTEN
FTX2EMPT
FTX1EMPT
FTX2FULL
FTX1FULL
LRI
FTX0EMPT
FRXEMPT
FTX0FULL
FRXFULL
TXDMAPAUSE
Bit
[17] Primary TX FIFOx under-run interrupt status. This is used
by interrupt clear bit. When this is high, you can clear
interrupt by writing '1'.
0 = Interrupt didn't be occurred.
1 = Interrupt was occurred.
[16] Primary TX FIFOx Under-run Interrupt Enable
0 = TXFIFO Under-run INT disable
1 = TXFIFO Under-run INT enable
[15] Primary TX FIFO2 empty Status Indication
0 = TX FIFO2 is not empty(Ready to transmit Data)
1 = TX FIFO2 is empty (Not Ready to transmit Data)
[14] Primary TX FIFO1 empty Status Indication
0 = TX FIFO1 is not empty (Ready to transmit Data)
1 = TX FIFO1 is empty (Not Ready to transmit Data)
[13] Primary TX FIFO2 full Status Indication
0 = TX FIFO2 is not full
1 = TX FIFO2 is full
[12] Primary TX FIFO1 full Status Indication
0 = TX FIFO1 is not full
1 = TX FIFO1 is full
[11] Left/Right channel clock indication. Note that LRI meaning
is dependent on the value of LRP bit of I2SMOD register.
0 = Left (when LRP bit is low) or right (when LRP bit is
high)
1 = Right (when LRP bit is low) or left (when LRP bit is
high)
[10] Primary Tx FIFO0 empty status indication.
0 = FIFO is not empty (ready for transmit data to channel)
1 = FIFO is empty (not ready for transmit data to channel)
[9] Rx FIFO empty status indication.
0 = FIFO is not empty
1 = FIFO is empty
[8] Primary Tx FIFO0 full status indication.
0 = FIFO is not full
1 = FIFO is full
[7] Rx FIFO full status indication.
0 = FIFO is not full (ready for receive data from channel)
1 = FIFO is full (not ready for receive data from channel)
[6] Tx DMA operation pause command for primary TX FIFOx.
Note that when this bit is activated, the DMA request will be
halted after current on-going DMA transfer is completed.
0 = No pause DMA operation for TX FIFOx
1 = Pause DMA operation for TX FIFOx
Description
2 IIS MULTI AUDIO INTERFACE
R/W Initial State
R/W 0
R/W 0
R 0
R 0
R 0
R 0
R 0
R 0
R 0
R 0
R 0
R/W 0
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