Samsung S5PC110 Manual page 1391

S5PC110_UM
5.1.6 BLOCK DIAGRAM OF INTEGRATION INFORMATION
S5PC110 S5PC110
Figure 5-2
The Clock Management Unit (CMU) comprises of two blocks: BUS_CLK (for bus interface part) and CORE_CLK
(for G3D internal function part). Both clocks are supported in 200Mhz clock domain, but you can set the two clocks
with different clocks. BUS_CLK and CORE_CLK can be fully asynchronous.
G3D block has six controllable clock domains partitioned internally to functional areas of the design. It
automatically controls clock gating if some blocks are not used at that time.
G3D block has its own power domain. If you do not use G3D block, then you can turn off the G3D block
thoroughly by setting PMU. The detail power states are summarized in
explanation of power mode in Chapter, "PMU".
Power
NORMAL
Mode
Power on/ Clock
G3D gating/ Power
gating
NOTE: KEEP power state in NORMAL mode means power-on G3D in NORMAL mode is still power-on, clock-gated G3D in
NORMAL mode is still clock-gated, and power-gated G3D in NORMAL mode is still power-gated.
Interconnect Interconnect
bus bus
CMU CMU
Interrupt controller Interrupt controller
Block Diagram of Integration Information with Related Block
Table 5-2 Power Mode Summary About G3D
IDLE
KEEP power
state in
NORMAL
(NOTE)
mode
SYS_BUS SYS_BUS
MEM_BUS MEM_BUS
BUS_CLK BUS_CLK
CORE_CLK CORE_CLK
RESETN RESETN
IRQ IRQ
Table
DEEP-IDLE
KEEP power
state in gating/
NORMAL mode/
Power gating
G3D G3D
5-2. You can see the detailed
DEEP-
STOP
STOP
Clock
Power
Power gating
gating
5 4BG3D
SLEEP
Power off
5-10