Samsung S5PC110 Manual page 1584

S5PC110_UM 9 8BMIXER
9.1.3 VIDEO CLOCK RELATION
Figure 9-2 TV Sub-System Block Diagram and Usage Frequency
There are two paths from mixer to TVENC and HDMI. It is selected exclusively at the Clock Controller (refer to
REG_DST_SEL at mixer_CFG register (0xF920_ 0004)). When TV-out is selected, Mixer I/F clock (VCLKHS) and
VCLKS (TVENC clock) is fixed by 54MHz. Thus, you must set MIXER_SEL register in CLK_SRC1(0xE010_0204)
for more information, refer to CMU chapter. Else, in HDMI-out selection, REG_DST_SEL register is configured
properly. Then, you set the same clock configuration between MIXER I/F clock (VCLKHS) and VCLKH(HDMI pixel
clock). The clock which is generated by embedded PLL in HDMI PHY must be selected using usage frequency
table (refer to VCLKHS(or VCLKH. You can configure clock source through CLK_SRC1 register.
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