Samsung S5PC110 Manual page 1398

S5PC110_UM
APB IF
APB IF
There are several internal masters in MFC core. Their interfaces are controlled by the bus arbiter. Internal masters
have an index[6:0] register controlled by firmware. This register may be used to generate address, which will be
an output of AXI interface.
After getting an index, the bus arbiter makes a decision which port to be used based on Index[6] (Index[6] = 0 for
Port_A and 1 for Port_B). With Index[5:0], the bus arbiter get a base address from Q-matrix SRAM. The real
address is calculated with the base address and DRAM_BASE_ADDR in AXI_MASTER. Therefore host must set
a base address before starting codec.
Full-HD MFC
RG
Arbiter
RISC
Figure 6-1
Base Addr SRAM
(Q-matrix SRAM)
RG
Bus Arbiter
AXI
Master I/F
Port_A
MFC Block Diagram
6 5BMULTI FORMAT CODEC
Search Shared
SRAM SRAM
MFC Core
AXI
Master I/F
Port_B
6-6