Samsung S5PC110 Manual page 1591

S5PC110_UM
9.2.2.4 MIXER_INT_STATUS Register (MIXER_INT_STATUS, R/W, Address = 0xF920_000C)
MIXER_INTR
Reserved
INT_CLEAR_VSYNC
INT_STATUS_VP
INT_STATUS_GRP1
INT_STATUS_GRP0
Reserved
INT_STATUS_VSYNC
Bit
[31:11] Reserved, read as zero, do not modify
[11] The vertical sync. inerrupt clear bit. ( Write only )
1 = Interrupt is cleared.
Write '1' to this bit clears the interrupt. Also, Write '1' to
this bit before you set INT_EN_VSYNC.
[10] The VP underflow interrupts status.
0 = Interrupt is not fired
1 = Interrupt is fired
Writing '1' to this bit clears the interrupt.
This interrupt is automatically asserted by line buffer
controller if underflow is generated in line buffer.
[9] The graphic layer1 line buffer underflow interrupt status.
0 = Interrupt is not fired
1 = Interrupt is fired
Writing '1' to this bit clears the interrupt.
This interrupt is automatically asserted by line buffer
controller if underflow is generated in line buffer.
[8] The graphic layer0 line buffer underflow interrupt status.
0 = Interrupt is not fired
1 = Interrupt is fired
Writing '1' to this bit clears the interrupt.
This interrupt is automatically asserted by line buffer
controller if underflow is generated in line buffer.
[7:1] Reserved, read as zero, do not modify
[0] The vertical sync. status. ( Read only )
0 = Interrupt is not fired.
1 = Interrupt is fired.
Note : If INT_STATUS_VSYNC & !INT_STATUS_VP
& !INT_STATUS_GRP1 & !INT_STATUS_GRP0 is high,
The vertical sync. is fired.
Description
9 8BMIXER
Initial State
0
0
0
0
0
0
9-11