Samsung S5PC110 Manual page 1706

Risc microprocessor
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S5PC110_UM
10.3.5.17 MUX Control Register (I2S_MUX_CH, R/W, Address = 0xFA14_0054)
I2S_MUX_CH
CH3_R_en
CH3_L_en
CH2_R_en
CH2_L_en
CH1_R_en
CH1_L_en
CH0_R_en
CH0_L_en
10.3.5.18 MUX Control Register (I2S_MUX_CUV, R/W, Address = 0xFA14_0058)
I2S_MUX_CUV
-
CUV_R_en
CUV_L_en
Bit
[7]
0 = Disables channel 3 right audio data output
1 = Enables channel 3 right audio data output
[6]
0 = Disables channel 3 left audio data output
1 = Enables channel 3 left audio data output
[5]
0 = Disables channel 2 right audio data output
1 = Enables channel 2 right audio data output
[4]
0 = Disables channel 2 left audio data output
1 = Enables channel 2 left audio data output
[3]
0 = Disables channel 1 right audio data output
1 = Enables channel 1 right audio data output
[2]
0 = Disables channel 1 left audio data output
1 = Enables channel 1 left audio data output
[1]
0 = Disables channel 0 right audio data output
1 = Enables channel 0 right audio data output
[0]
0 = Disables channel 0 left audio data output
1 = Enables channel 0 left audio data output
Bit
[7:2]
Reserved
[1]
0 = Disables right channel CUV data
1 = Enables right channel CUV data
[0]
0 = Disables left channel CUV data
1 = Enables left channel CUV data
10 9BHIGH-DEFINITION MULTIMEDIA INTERFACE
Description
Description
Initial State
0
0
0
0
0
0
1
1
Initial State
6b000000
1
1
10-97

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