Samsung S5PC110 Manual page 1546

S5PC110_UM
8.4.1.1 Video Processor Enable/Disable Control Register (VP_ENABLE, Address = 0xF910_0000)
VP_ENABLE
Reserved
VP_ON_S
VP_OPERATION
_STATUS
VP_ON
8.4.1.2 Video Processor Software Reset (VP_SRESET, R/W, Address = 0xF910_0004)
VP_SRESET
Reserved
VP_SRESET
Bit
[31:3] Reserved, read as zero, do not modify
[2] This bit is read-only. Shadow bit of the bit [0]
[1] This bit is read-only.
0 = VP is operating.
1 = VP is idle mode.
[0] This bit is read-write.
0 = Disables
1 = Enables
Note: The SFRs of Video Processor and Image Mixer is
updated by Vertical Sync of TVENC's Timing Generator.
Thus, SFRs are configured before this bit is enabled.
The sequence to enable TVSS is as follows: "VP ->
MIXER TVENC(HDMI)".
Also, because SFRs are updated by Verical Sync, the
disabling sequence is following as : "VP -> MIXER ->
TVNEC(HDMI)".
Bit
[31:1] Reserved, read as zero, do not modify
[0] 0 = Software reset is set and the last soft reset is complete.
1 = VP is processing software reset sequence.
Description
Description
8 7BVIDEO PROCESSOR
R/W Initial State
R/W 0
R 0
R 1
R/W 0
Initial State
0
0
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