Samsung S5PC110 Manual page 1636

S5PC110_UM
Register
SPDIFIN_Pc_INFO_
1
SPDIFIN_Pc_INFO_
2
SPDIFIN_Pd_INFO_
1
SPDIFIN_Pd_INFO_
2
SPDIFIN_DATA_BU
F_0_1
SPDIFIN_DATA_BU
F_0_2
SPDIFIN_DATA_BU
F_0_3
SPDIFIN_USER_BU
F_0
SPDIFIN_DATA_BU
F_1_1
SPDIFIN_DATA_BU
F_1_2
SPDIFIN_DATA_BU
F_1_3
SPDIFIN_USER_BU
F_1
I2S Registers
I2S_CLK_CON
I2S_CON_1
I2S_CON_2
I2S_PIN_SEL_0
I2S_PIN_SEL_1
I2S_PIN_SEL_2
I2S_PIN_SEL_3
I2S_DSD_CON
I2S_IN_MUX_CON
I2S_CH_ST_CON
I2S_CH_ST_0
Address R/W
0xFA13_0050 R
0xFA13_0054 R
0xFA13_0058 R
0xFA13_005C R
0xFA13_0060 R
0xFA13_0064 R
0xFA13_0068 R
0xFA13_006C R
0xFA13_0070 R
0xFA13_0074 R
0xFA13_0078 R
0xFA13_007C R
0xFA14_0000 R/W
0xFA14_0004 R/W
0xFA14_0008 R/W
0xFA14_000C R/W
0xFA14_0010 R/W
0xFA14_0014 R/W
0xFA14_0018 R/W
0xFA14_001C R/W
0xFA14_0020 R/W
0xFA14_0024 R/W
0xFA14_0028 R/W
10 9BHIGH-DEFINITION MULTIMEDIA INTERFACE
Description
Specifies the SPDIFIN PC info register 1.
Specifies the SPDIFIN PC info register 2.
Specifies the SPDIFIN PD info register 1.
Specifies the SPDIFIN PD Info Register 2.
Specifies the SPDIFIN data buffer register
0_1.
Specifies the SPDIFIN data buffer register
0_2.
Specifies the SPDIFIN data buffer register
0_3.
Specifies the SPDIFIN user buffer register 0.
Specifies the SPDIFIN data buffer register
1_1.
Specifies the SPDIFIN data buffer register
1_2.
Specifies the SPDIFIN data buffer register
1_3.
Specifies the SPDIFIN user buffer register 1.
Specifies the I2S clock enable register.
Specifies the I2S control register 1.
Specifies the I2S control register 2.
Specifies the I2S input pin selection register
0.
Specifies the I2S input pin selection register
1.
Specifies the I2S input pin selection register
2.
Specifies the I2S input pin selection register
3.
Specifies the I2S DSD control register.
Specifies the I2S In/ Mux control register.
Specifies the I2S channel status control
register.
Specifies the I2S channel status block 0.
Reset Value
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x16
0x77
0x77
0x77
0x07
0x02
0x60
0x00
0x00
10-27