Samsung S5PC110 Manual page 1821

S5PC110_UM
SCLK_AUDIO0
DIV
(1 ~ 16)
EPLL
Clock Controller in
Audio Sub - System
External I2S Clock
shows the route of the root clock with setting in IIS clock control block and system controller. RCLK
Figure 2-3
indicates root clock and RCLKSRC chooses a clock source of RCLK between AUDIO BUS CLK and I2SCLK. The
IIS pre-scaler (clock divider) is employed to generate a root clock with divided frequency from source clock.
In master mode, the root clock is divided to generate I2SSCLK and I2SLRCLK. In slave mode, this clock is not
used to generate I2SSCLK and I2SLRCLK.
CDCLKCON controls direction of CDCLK GPIO pad. The direction is set by CDCLKCON SFR bit (IISMOD[12]).
When CDCLKCON SRF bit is 0, auxiliary clock out is supported for Codec chip at both cases of Master/Slave
mode. In this case, RCLK can be supplied to external IIS CODEC chip. When CDCLKCON SRF bit is 1, External
I2S clock is supplied from external device. This is useful when internal clock sources are not adequate for
generating exact I2SSCLK and I2SLRCLK.
IIS
AUDIO
BUS CLK
I2 SCLK
RCLKSRC =
IISMOD{ 10]
Figure 2-3
RCLK
1/M
1/ N
Pre - scaler
IIS Clock Control Block Diagram
2 IIS MULTI AUDIO INTERFACE
BCLKmaster
CDCLKCON
CODECLKO
PAD
2-4