Samsung S5PC110 Manual page 1374

S5PC110_UM
4.6.1.1 Control Register (CSIS_CONTROL, R/W, Address = 0xFA60_0000)
CSIS_CONTROL
S_DpDn_Swap_Clk
S_DpDn_Swap_Dat
Reserved
Parallel
Reserved
Update_Shadow
Reserved
WCLK_Src
Reserved
SwRst
Reserved
Enable
Bit
[31] Swaps Dp channel and Dn channel of clock lanes.
0 = Default
1 = Swaps
[30] Swaps Dp channel and Dn channel of data lanes.
0 = Default
1 = Swaps
[29:21] Should be 0.
[20] Specifies data alignment size. Refer to
0 = 24-bit data alignment
1 = 32-bit data alignment
[19:17] Should be 0.
[16] Updates the shadow registers.
0 = Default
1 = Updates the shadow registers
After configuration, set this bit for updating shadow registers.
This bit is cleared automatically after updating shadow
registers.
[15:9] Should be 0.
[8] Specifies wrapper clock source.
0 = PCLK
1 = EXTCLK
This bit determines the source of pixel clock, which transfers
image data to CAMIF.
[7:5] Should be 0.
[4] Specifies software reset.
0 = No reset
1 = Reset
All writable registers in CSIS return to their reset value. After
this bit is active for three cycles, this bit is de-asserted
automatically.
Note: Almost all MIPI CSIS blocks use "ByteClk" from D-
PHY. "ByteClk" is not a continuous clock. You must assert
software reset if the camera module is turned off.
[3:1] Reserved
[0] Specifies the CSIS system on/ off.
0 = Off
1 = On
If this bit is low even though the CSIS clock is alive, then any
request from CSIS is not serviced and kept waiting. Once the
main host disables CSIS, it should be reset by software or
hardware before the main host enables CSIS again.
Description
4.4 "Data
4 3BMIPI CSIS
Initial State
0
0
0
1
Format".
0
0
0
0
0
0
0
0
4-7