Samsung S5PC110 Manual page 1419

S5PC110_UM
6.3.2.3 Memory Controller Registers
6.3.2.3.1 Channel A DRAM Base Address Register (MFC_MC_DRAMBASE_ADDR_A, R/W, Address =
0xF170_0508)
MFC_MC_DRAMBASE_
ADDR_A
MC_DRAMBASE_ADDR_A
Reserved
6.3.2.3.2 Channel B DRAM Base Address Register (MFC_MC_DRAMBASE_ADDR_B, R/W, Address =
0xF170_050C)
MFC_MC_DRAMBASE_
ADDR_B
MC_DRAMBASE_ADDR_B
Reserved
6.3.2.3.3 MC (Memory Controller) Status Register (MFC_MC_STATUS, R, Address = 0xF170_0510)
MFC_MC_STATUS
Reserved
MC_BUSY_B
MC_BUSY_A
NOTE: X stands for undetermined.
Bit
[31:17] The DRAM base address must be aligned at
128KByte. MFC's access range through port A is
from DRAMBASE_ADDR_A to DRAMBASE_ADDR_A
+ 256MByte
[16:0] Reserved
Bit
[31:17] The DRAM base address must be aligned at
128KByte. MFC's access range through port B is
from DRAMBASE_ADDR_B to DRAMBASE_ADDR_B
+ 256MByte
[16:0] Reserved
Bit
[31:2] Not used
[1] Busy at port B
0 = Idle
1 = Busy
[0] Busy at port A
0 = Idle
1 = Busy
Description
Description
Description
6 5BMULTI FORMAT CODEC
Initial State
0x6980
0
Initial State
0x1180
0
Initial State
0
X
X
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