Samsung S5PC110 Manual page 1720

S5PC110_UM
10.3.6.47 CEC Configure Register (CEC_TX_STATUS_0, R, Address = 0xE1B0_0000)
CEC_TX_STATUS_0
-
Tx_Error
Tx_Done
Tx_Transferring
Tx_Running
10.3.6.48 CEC Configure Register (CEC_TX_STATUS_1, R, Address = 0xE1B0_0004)
CEC_TX_STATUS_1
Tx_Bytes_Transferred
Bit
[7:4] Reserved
[3] Specifies the CEC Tx_Error interrupt flag. This bit field
also specifies the status of Tx_Error interrupt and is valid
only if Tx_Done bit is set.
0 = No error occurs
1 = An error occurs during CEC Tx transfer
It will be cleared
- if set to 0 by Tx_Enable bit of CEC_TX_CTRL register
- if set Clear_Intr_Tx_Done or Clear_Intr_Tx_Error bit in
CEC_INTR_CLEAR register
[2] Specifies the CEC Tx_Done interrupt flag. This bit field
also specifies the status of Tx_Done interrupt.
0 = Running or idle
1 = Finishes CEC Tx transfer
It will be cleared
- if Tx_Enable bit of CEC_TX_CTRL_0 is reset
- if Clear_Intr_Tx_Done or Clear_Intr_Tx_Error bit
in CEC_INTR_CLEAR register is set
[1] If TX-Running is set, this field is valid.
0 = Tx waits for the CEC Bus
1 = CEC Tx transfers data via CEC Bus
[0] 0 = Tx Idle
1 = Enables CEC Tx, and waits for the CEC bus or
transfers the message.
Bit
[7:0] Specifies the number of blocks transferred (1 byte = 1
block in a CEC message). After sending the CEC
message, this field will be updated. It will be cleared if
Clear_Intr_Tx_Done or Clear_Intr_Tx_Error bit is set in
CEC_Intr_Clear register.
10 9BHIGH-DEFINITION MULTIMEDIA INTERFACE
Description
Description
Initial State
4b0000
0
0
0
0
Initial State
0
10-111