Samsung S5PC110 Manual page 1551

S5PC110_UM
8.4.1.9 Video Processor Bottom Luminance Picture Pointer Control Register (VP_BOT_Y_PTR, R/W,
Address = 0xF910_002C)
VP_TOP_C_PTR
VP_BOT_Y_PTR
8.4.1.10 Video Processor Top Chrominance Picture Pointer Control Register (VP_TOP_C_PTR, R/W,
Address = 0xF910_0030)
VP_CR_PTR
VP_TOP_C_PTR
8.4.1.11 Video Processor Bottom Chrominance Picture Pointer Control Register (VP_BOT_C_PTR, R/W,
Address = 0xF910_0034)
VP_BOT_Y_PTR
VP_BOT_C_PTR
Bit
[31:0] Base address for luminance of bottom field.
It should be integer multiples of 8.
(LSB[2:0] must be 3'b000)
If TILE mode is enable,
VP_BOT_Y_PTR = VP_TOP_Y_PTR + 0x40
Bit
[31:0] Base address for chrominance of top field.
It should be integer multiples of 8.
(LSB[2:0] must be 3'b000)
Bit
[31:0] Base address for chrominance of bottom field.
It should be integer multiples of 8.
(LSB[2:0] must be 3'b000)
If TILE mode is enable,
VP_BOT_C_PTR = VP_TOP_C_PTR + 0x40
Description
Description
Description
8 7BVIDEO PROCESSOR
Initial State
0
Initial State
0
Initial State
0
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