Samsung S5PC110 Manual page 1860

S5PC110_UM
3.5.4 EXAMPLE CODE
3.5.4.1 Tx Channel
The I2S TX channel provides a single stereo compliant output. The transmit channel can operate in master or
Slave mode. Data is transferred between the processor and the I2S controller via an APB access or a DMA
access.
The processor must write words in multiples of two (i.e. for left and right audio sample).The words are serially
shifted out timed with respect to the audio serial bitclk, SCLK and word select clock, LRCLK.
TX Channel has 64X32-bit wide FIFO where the processor or DMA can write upto 16 left/right data samples
After enabling the channel for transmission.
An Example sequence is as follows:
Ensure the PCLK and CDCLK are coming correctly to the I2S controller and FLUSH the TX FIFO using the
TFLUSH bit in the Please ensure that I2S Controller is configured in one of the following modes.
• TX only mode
• TX/RX simultaneous mode
The Data is aligned in the TX FIFO for 8-bits/channel or 16-bits/channel BLC as shown in
31
Right Channel
Figure 3-4 TX FIFO Structure for BLC = 00 or BLC = 01
BLC = 00
16 15
Left Channel
3 IIS-BUS INTERFACE
Figure 3-4.
BLC = 01
7
0
LOC 0
LOC 1
LOC 2
LOC 3
LOC 4
LOC 5
LOC 6
LOC 7
LOC 8
LOC 9
LOC 10
LOC 11
LOC 12
LOC 13
LOC 14
LOC 15
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