Samsung S5PC110 Manual page 1723

S5PC110_UM
10.3.6.52 CEC Configure Register (CEC_INTR_CLEAR, R/W, Address = 0xE1B0_0014)
CEC_INTR_CLEAR
-
Clear_Intr_Rx_Error
Clear_Intr_Rx_Done
-
Clear_Intr_Tx_Error
Clear_Intr_Tx_Done
10.3.6.53 CEC Configure Register (CEC_LOGIC_ADDR, R/W, Address = 0xE1B0_0020)
CEC_LOGIC_ADDR
-
Logic_Addr
10.3.6.54 CEC Configure Register (CEC_ DIVISOR_0 ~ CEC_ DIVISOR_3, R/W, Address = 0xE1B0_0030)
CEC_ DIVISOR_0~
CEC_ DIVISOR_3
CEC_Divisor
Bit
[7:6] Reserved
[5] Specifies the Rx_Error interrupt clear bit.
0 = No effect
1 = Clears Rx_Error and Rx_Bytes_Received fields in
CEC_RX_STATUS_0 and 1 registers. It will be cleared
after one clock.
[4] Specifies the Rx_Done interrupt clear bit.
0 = No effect
1 = Clears Rx_Done and Rx_Bytes_Received fields in
CEC_RX_STATUS_0 and 1 registers. Resets to 0 after
one clock.
[3:2] Reserved
[1] Specifies the Tx_Error interrupt clear bit.
0 = No effect
1 = Clears Tx_Error and Tx_Bytes_Received fields in
CEC_TX_STATUS_0 and 1 registers. Resets to 0 after
one clock.
[0] Specifies the Tx_Done interrupt clear bit.
0 = No effect
1 = Clears Tx_Done and Tx_Bytes_Received fields in
CEC_TX_STATUS_0 and 1 registers. Resets to 0 after
one clock.
Bit
[7:4] Reserved
[3:0] Specifies the HDMI Tx logical address (0~15).
Bit
[7:0] Specifies the divisor used in counting 0.05ms period. This
divisor should satisfy the following equation:
(CEC_DIVISOR+1) x (clock cycle time(ns)) = 0.05ms
Note: To apply CEC_Divisor, it should be '0' for Tx_Reset
and Rx_Reset, while Tx_Start and Rx_Start are '0'.
10 9BHIGH-DEFINITION MULTIMEDIA INTERFACE
Description
Description
Description
Initial State
2b00
0
0
2b00
0
0
Initial State
4b0000
4b0000
Initial State
0
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