Samsung S5PC110 Manual page 1833

S5PC110_UM
2.7.4.2 RX Channel
The IIS RX channel provides a single stereo compliant output. The receive channel can operate in master or slave
mode. Data is received from the input line and transferred into the RX FIFO. The processor can then read this
data via an APB read or a DMA access can access this data.
RX Channel has 64 X 32-bit wide RX FIFO where the processor or DMA can read upto 16 left/right data samples
after enabling the channel for reception.
An Example sequence is as follows:
Ensure the Audio bus clock and CDCLK are coming correctly to the IIS controller and FLUSH the RX FIFO using
the RFLUSH bit in the I2SFIC Register (IIS FIFO Control Register) and the I2S controller is configured in any of
the modes
• Receive only.
• Receive/Transmit simultaneous mode
This can be done by Programming the TXR bit in the I2SMOD Register (IIS Mode Register)
1. Then Program the following parameters according to the need
− MSS, RCLKSRC
− SDF
− BFS
− BLC
− LRP
For Programming, the above mentioned fields please refer I2SMOD Register (IIS Mode Register)
2. Once ensured that the input clocks for IIS controller are up and running and step 1 and 2 have been
completed user must put the I2SACTIVE high to enable any reception of data, the IIS Controller
receives data on the LRCLK change.
The Data must be read from the RX FIFO using the I2SRXD Register (IIS RX FIFO Register) only after looking
at the RX FIFO count in the I2SFIC Register (IIS FIFO Control Register). The count would only increment
once the complete left channel and right have been received. The Data is aligned in the RX FIFO for 8-
bits/channel or 16-bits/channel BLC as shown in .
Figure 2-9
2 IIS MULTI AUDIO INTERFACE
2-16