Samsung S5PC110 Manual page 1684

S5PC110_UM
10.3.4 SPDIF REGISTER
10.3.4.1 SPDIF Register (SPDIFIN_CLK_CTRL, R/W, Address = 0xFA13_0000)
SPDIFIN_CLK_CTRL
-
ready_clk_down
power_on
The spdif_clk is gated by an external clock gating module for low-power. Disabling the clock should not cause
stalling of HDMI data transfer. Therefore, the system processor requests disabling of the clock by setting the
power_on register to low and the module acknowledges this request by setting the ready_clk_down register to
high after a current transaction on the I2C bus, and HDMI is finished. The module must not commence a new bus
transaction until the system processor sets the power_on register to high again.
The system processor switches off clk_xx when the ready_clk_down bit is one and the power_on bit is zero.
The system processor switches on the clock at any time. After having switched on clk_xx, the system processor
sets the power_on bit to 1, which forces the ready_clk_down bit to zero.
Once the reset clock of SPDIFIN is switched off, the power_on bit is set to zero and the ready_clk_down bit is set
to one.
Bit
[7:2] Reserved
[1] 0 = Enables clock
1 = Readies for disabling clock (default)
[0] 0 = Disables clock (default)
1 = Activates clock
If this bit is reset, SPDIFIN stops checking the input signal
just before the next 'subframe' of SPDIF signal format
and waits for the 'acknowledge' signal from HDMI for
unresolved previous 'request' towards HDMI. It then
asserts 'ready_clk_down' as high.
To initialize internal states, assert software reset, that is,
SPDIFIN_OP_CTRL. op_ctrl=00b right after activating
clock again.
clk
Control by system
processor
power_
on
pwrdwn_req
SPDIFIN
core
Figure 10-13 Structure of Power Down Circuit
10 9BHIGH-DEFINITION MULTIMEDIA INTERFACE
Description
Clock gating
clk_xx
ready
_clk_down
&
pwrdwn_ack
Initial State
6b000000
1
0
10-75