Samsung S5PC110 Manual page 1862

S5PC110_UM
3.5.4.2 RX Channel
The I2S RX channel provides a single stereo compliant output. The receive channel can operate in master or
slave mode. Data is received from the input line and transferred into the RX FIFO. The processor can then
read this data via an APB read or a DMA access can access this data.
RX Channel has a 64X32-bit wide RX FIFO where the processor or DMA can read UPTO 16 left/right data
samples after enabling the channel for reception.
An Example sequence is as follows:
Ensure the PCLK and CDCLK are coming correctly to the I2S controller and FLUSH the RX FIFO using the
RFLUSH bit in the I2SFIC Register (I2S FIFO Control Register) and the I2S controller is configured in any of the
modes
• Receive only.
• Receive/Transmit simultaneous mode
This can be done by Programming the TXR bit in the I2SMOD Register (I2S Mode Register)
1. Then Program the following parameters according to the need
− MMS, RCLKSRC
− SDF
− BFS
− BLC
− LRP
For Programming, the above mentioned fields please refer I2SMOD Register (I2S Mode Register)
2. Once ensured that the input clocks for I2S controller are up and running and step 1 and 2 have been
completed user must put the I2SACTIVE high to enable any reception of data, the I2S Controller receives
data on the LRCLK change.
Read the data from the RX FIFO using the I2SRXD Register (I2S RX FIFO Register) after looking at the RX FIFO
count in the I2SFIC Register (I2S FIFO Control Register). The count would only increment once the complete left
channel and right have been received.
3 IIS-BUS INTERFACE
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