Samsung S5PC110 Manual page 1690

S5PC110_UM
SPDIFIN_CONFIG_1
U_V_C_P_report
-
data_align
10.3.4.6 SPDIF Register (SPDIFIN_CONFIG_2, R/W, Address = 0xFA13_0014)
SPDIFIN_CONFIG_2
-
clk_divisor
Bit
[2] 0 = Neglects 'user_bit', 'validity_bit', 'channel status', and
'parity_bit' of SPDIF format.
1 = Reports 'user_bit', 'validity_bit', 'channel status', and
'parity_bit' of SPDIF format
The report will be delivered via HDMI for each sub-frame.
Valid only if SPDIFIN_CONFIG. data_align is set for 32-bit
mode. For more information, see
SPDIFIN_DATA_BUF_x.
[1] Reserved (Must be '1')
[0] 0 = 16-bit mode
1 = 32-bit mode
16-bit: Only takes 16-bits from MSB in a sub-frame of
SPDIF format, and then concatenates two consecutive
16-bit data in one 32-bit register of
SPDIFIN_DATA_BUF_x.
32-bit: Only takes data from one subframe with zero
padding to MSB part. For example, 0x00ffffff for 24-bit
data.
With stream mode, set 'word_length_value_mode' as 1
and set SPDIFIN_USER_VALUE.word_length_manual as
3b000.
- These two modes will be applied to both modes of
SPDIFIN_CONFIG.data_type, that is, PCM or stream. For
more information, see SPDIFIN_DATA_BUF_x.
Bit
[7:4] Reserved
[3:0] SPDIFIN_internal_clock = system_clock / (clk_divisor + 1)
(SPDIFIN_internal_clock ≤ 135 Mhz)
SPDIFIN over-samples the SPDIF input signal with
internal clock that is divided from system clock.
Recommended over-sampling ratio is 8~10, thus the
following calculation holds:
Recommended SPDIFIN_internal_clock
= Sampling Frequency of SPDIF Input Signal * 64-bits *
10 times over-sampling
For example, 48 kHz * 64-bits * 10 times over-sampling =
31 Mhz.
10 9BHIGH-DEFINITION MULTIMEDIA INTERFACE
Description
Description
Initial State
0
1
0
Initial State
0x0
0x0
10-81