Samsung S5PC110 Manual page 2029

S5PC110_UM
Table 1-12 TFT LCD Controller Module Signal Timing Constants
(VDDINT = 1.1V ± 5%, TA = -25 to 85°C, VDDlcd = 1.7V - 3.6V)
Parameter
VCLK pulse width
VCLK pulse width high
VCLK pulse width low
Vertical sync pulse width
Vertical back porch delay
Vertical front porch dealy
Hsync setup to VCLK falling edge
VDEN setup to VCLK falling edge
VDEN hold from VCLK falling edge
VD setup to VCLK falling edge
VD hold from VCLK falling edge
VSYNC setup to HSYNC falling edge
VSYNC hold from HSYNC falling edge
NOTE:
1. VCLK period
2. HSYNC period
Symbol Minimum
Tvclk
Tvclkh
Tvclkl
Tvspw VSPW + 1
Tvbpd VBPD+1
Tvfpd VFPD+1
Tl2csetup
Tde2csetup
Tde2chold
Tvd2csetup
Tvd2chold
Tf2hsetup HSPW + 1
Tf2hhold HBPD + HFPD +
HOZVAL + 3
Typical
12 -
0.3 -
0.3 -
-
-
-
0.3 -
0.3 -
0.3 -
0.3 -
0.3 -
-
-
1 ELECTRICAL DATA
Maximum Unit
- ns
(1)
-
Pvclk
- Pvclk
(2)
-
Phclk
- Phclk
- Phclk
- Pvclk
- Pvclk
- Pvclk
- Pvclk
- Pvclk
- Pvclk
- Pvclk
1-22