Samsung S5PC110 Manual page 1900

S5PC110_UM
5.6.1.2 PCM CLK Control Register (PCM_CLKCTL)
• PCM_CLKCTL, R/W, Address = 0xE230_0004
• PCM_CLKCTL, R/W, Address = 0xE120_0004
• PCM_CLKCTL, R/W, Address = 0xE2B0_0004
The bit definitions for the PCM_CTL Control Register are described below:
PCM_CLKCTL
Reserved
CTL_SERCLK_EN
CTL_SERCLK_SEL
SCLK_DIV
SYNC_DIV
5.6.1.3 The PCM Tx FIFO Register ( PCM_TXFIFO)
• PCM_TXFIFO, R/W, Address = 0xE230_0008
• PCM_TXFIFO, R/W, Address = 0xE120_0008
• PCM_TXFIFO, R/W, Address = 0xE2B0_0008
The bit definitions for the PCM_TXFIFO Register are described below:
PCM_TXFIFO
Reserved
TXFIFO_DVALID
TXFIFO_DATA
Bit
[31:20] Reserved
[19] Enables the serial clock division logic.
Must be HIGH for the PCM to operate
[18] Selects the source of the serial clock
0 = SCLK_AUDIO0,1,2(PCM0, PCM1, PCM2)
1 = PCLK
[17:9] Controls the divider used to create the PCMSCLK based
on the PCMCODEC_CLK
Final clock will be source_clk / 2*(sclk_div+1)
[8:0] Controls the frequency of the PCMSYNC signal based on
the PCMSCLK.
Bit
[31:17] Reserved
[16] TXFIFO data is valid
Write: Not valid
Read: TXFIFO read data valid
1 = Valid
0 = Invalid (probably read an empty fifo)
[15:0] TXFIFO DATA
Write: TXFIFO_DATA is written into the TXFIFO
Read: TXFIFO is read using the APB interface
Note: reading the TXFIFO is meant to support debugging.
Online the TXFIFO is read by the PCM serial shift engine,
not the APB
Description
Description
5 PCM AUDIO INTERFACE
Initial State
0
0
0
000
000
Initial State
0
1
0
5-9