Samsung S5PC110 Manual page 1802

Figure
Number
Figure 1-1 Block Diagram of Audio Subsystem ................................................................................................. 1-3
Figure 1-2 Audio Subsystem Block Diagram ..................................................................................................... 1-4
Figure 1-3 Clock Controller in Audio Subsystem ............................................................................................... 1-5
Figure 2-1 IIS-Bus Block Diagram...................................................................................................................... 2-2
Figure 2-2 Clock Controller in Audio Sub-System ............................................................................................. 2-3
Figure 2-3 IIS Clock Control Block Diagram ...................................................................................................... 2-4
Figure 2-4 Master/Slave Modes of IIS................................................................................................................ 2-5
Figure 2-5 Concept of Mixer in IIS ..................................................................................................................... 2-7
Figure 2-6 IIS Audio Serial Data Formats .......................................................................................................... 2-9
Figure 2-7 TX FIFO Structure for BLC = 00 or BLC = 01................................................................................. 2-14
Figure 2-8 TX FIF0 Structure for BLC = 10 (24-bit/channel)............................................................................ 2-15
Figure 2-9 RX FIFO Structure for BLC = 00 or BLC = 01 ................................................................................ 2-17
Figure 2-10 RX FIF0 Structure for BLC = 10 (24-bit/channel) ........................................................................... 2-18
Figure 3-1 IIS-Bus Block Diagram...................................................................................................................... 3-2
Figure 3-2 IIS Clock Control Block Diagram ...................................................................................................... 3-3
Figure 3-3 IIS Audio Serial Data Formats .......................................................................................................... 3-5
Figure 3-4 TX FIFO Structure for BLC = 00 or BLC = 01................................................................................... 3-9
Figure 3-5 TX FIF0 Structure for BLC = 10 (24-bit/channel)............................................................................ 3-10
Figure 3-6 RX FIFO Structure for BLC = 00 or BLC = 01 ................................................................................ 3-12
Figure 3-7 RX FIF0 Structure for BLC = 10 (24-bits/channel) ......................................................................... 3-13
Figure 4-1 AC97 Block Diagram ........................................................................................................................ 4-2
Figure 4-2 Internal Data Path............................................................................................................................. 4-3
Figure 4-3 AC97 Operation Flow Chart.............................................................................................................. 4-4
Figure 4-4 Bi-directional AC-link Frame with Slot Assignments......................................................................... 4-5
Figure 4-5 AC-link Output Frame ....................................................................................................................... 4-6
Figure 4-6 AC-link Input Frame.......................................................................................................................... 4-8
Figure 4-7 AC97 Power-down Timing ................................................................................................................ 4-9
Figure 4-8 AC97 Power down/Power up Flow ................................................................................................. 4-10
Figure 4-9 AC97 State Diagram....................................................................................................................... 4-11
Figure 5-1 PCM timing, POS_MSB_WR/RD = 0 ............................................................................................... 5-3
Figure 5-2 PCM timing, POS_MSB_WR/RD = 1 ............................................................................................... 5-4
Figure 5-3 Input Clock Diagram for PCM ........................................................................................................... 5-4
Figure 6-1 Block Diagram of SPDIFOUT ........................................................................................................... 6-2
Figure 6-2 SPDIF Frame Format ....................................................................................................................... 6-3
Figure 6-3 SPDIF Sub-frame Format ................................................................................................................. 6-4
Figure 6-4 Channel Coding ................................................................................................................................ 6-5
Figure 6-5 Format of Burst Payload ................................................................................................................... 6-6
Figure 7-1 ADC and Touch Screen Interface Functional Block Diagram .......................................................... 7-3
Figure 7-2 ADC and Touch Screen Operation Signal........................................................................................ 7-7
Figure 7-3 Input Clock Diagram for ADC & Touch Screen Interface ................................................................. 7-8
Figure 8-1 Key Matrix Interface External Connection Guide.............................................................................. 8-2
Figure 8-2 Internal Debouncing Filter Operation................................................................................................ 8-3
Figure 8-3 Keypad Scanning Procedure ............................................................................................................ 8-5
Figure 8-4 Keypad Scanning Procedure II ......................................................................................................... 8-6
Figure 8-5 Keypad Scanning Procedure III ........................................................................................................ 8-6
Figure 8-6 Keypad Scanning Procedure when the two-key Pressed with Different Row .................................. 8-7
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