Samsung S5PC110 Manual page 1375

S5PC110_UM
4.6.1.2 D-PHY Control Register (CSIS_DPHYCTRL, R/W, Address = 0xFA60_0004)
This register controls D-PHY.
CSIS_DPHYCTRL
Reserved
DPHYOn
4.6.1.3 Configuration Register (CSIS_CONFIG, R/W, Address = 0xFA60_0008)
CSIS_CONFIG
Hsync_LIntv
Vsync_SIntv
Vsync_EIntv
DataFormat[5:0]
NumOfDatLane
Bit
[31:4] Should not change the value.
[4:0] Enables D-PHY clock and data lane.
[4]: Data lane 3
[3]: Data lane 2
[2]: Data lane 1
[1]: Data lane 0
[0]: Clock lane
0 = Disables
1 = Enables
Bit
[31:26] Specifies the interval between Hsync falling and Hsync rising
(Line interval). As shown in
interval.
6'h00 ~ 6'h3F cycle of Pixel clock.
[25:20] Specifies the interval between Vsync rising and first Hsync
rising. As shown in
6'h00 ~ 6'h3F cycle of Pixel clock
[19:8] Specifies the interval between last Hsync falling and Vsync
falling. As shown in
12'h000 ~ 12'hFFF cycle of Pixel clock
[7:2] Specifies the image data format.
0x1E = YUV422 (8-bit)
0x2A = RAW8
0x2B = RAW10
0x2C = RAW12
0x30 = user defined 1
0x31 = user defined 2
0x32 = user defined 3
0x33 = user defined 4
Others = Reserved
[1:0] Specifies the number of data lanes.
00 = 1 Data Lane
01 = 2 Data Lane
10 = 3 Data Lane
11 = 4 Data Lane
Description
Description
4-2, t2 specifies this
Figure
4-2, t1 specifies this interval.
Figure
4-2, t5 specifies this interval.
Figure
4 3BMIPI CSIS
Initial State
0
0
Initial State
0
0
0
0
0
4-8