Samsung S5PC110 Manual page 1782

S5PC110_UM
13.5.2 GENERAL REGISTERS
13.5.2.1 Software Reset Register (SOFT_RESET_REG, W, Address = 0xFA00_0000)
SOFT_RESET_REG
Reserved
R
13.5.2.2 Interrupt Enable Register (INTEN_REG, R/W, Address = 0xFA00_0004)
INTEN_REG
Reserved
INT_TYPE
CF
13.5.2.3 Interrupt Pending Register (INTC_PEND_REG, R/W, Address = 0xFA00_000C)
INTC_PEND_REG
Reserved
INTP_CMD_FIN
13.5.2.4 FIFO Status Register (FIFO_STAT_REG, R, Address = 0xFA00_0010)
FIFO_STAT_REG
Reserved
CMD_FIN
Bit
[31:1] Reserved
[0] Software Reset
Write to this bit results in a one-cycle reset signal to
FIMG2D graphics engine. Every command register and
parameter setting register will be assigned the "Reset
Value",
Bit
[31:1] Reserved
[1] Must be set to 0 (cannot be 1)
[0] Command Finished interrupt enable.
If this bit is set, when the graphics engine finishes the
execution of command, an interrupt occurs, and the
INTP_CMD_FIN flag in INTC_PEND_REG will be set.
Bit
[31:1] Reserved
[0] Command Finished interrupt flag.
Writing '1' to this bit clears this flag
It is recommended to clear this bit before Start_BitBLT
because of previous Start_BitBLT's residue
Bit
[31:1] Reserved
[0] 1 = The graphics engine finishes the execution of command.
0 = In the middle of rendering process.
Description
Description
Description
Description
13 12BG2D
Initial State
0x0
0x0
Initial State
0x0
0x0
0x0
Initial State
0x0
0x0
Initial State
0x0
0x1
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