Samsung S5PC110 Manual page 1402

S5PC110_UM
6.3 REGISTER DESCRIPTION
6.3.1 REGISTER MAP
Register
Control Registers
MFC_SW_RESET
MFC_RISC_HOST_INT
MFC_HOST2RISC_
COMMAND
MFC_HOST2RISC_ARG1
MFC_HOST2RISC_ARG2
MFC_HOST2RISC_ARG3
MFC_HOST2RISC_ARG4
MFC_RISC2HOST_
COMMAND
MFC_RISC2HOST_ARG1
MFC_RISC2HOST_ARG2
MFC_RISC2HOST_ARG3
MFC_RISC2HOST_ARG4
MFC_FIRMWARE_
VERSION
DBG_INFO_OUTPUT1
DBG_INFO_OUTPUT1
MFC_FIRMWARE_STAT
US
MFC_MC_DRAMBASE_
ADDR_A
Address R/W
0xF170_0000 R/W Soft reset for each module in MFC. Each
0xF170_0008 R/W MFC to host interrupt register.
0xF170_0030 R/W Host to MFC command register.
0xF170_0034 R/W The first argument of the host command
0xF170_0038 R/W The second argument of the host command
0xF170_003C R/W Context memory address
0xF170_0040 R/W Context memory size
0xF170_0044 R/W MFC to host command register.
0xF170_0048 R/W MFC to host argument register.
0xF170_004C R/W The second argument of the host command
0xF170_0050 R/W The Third argument of the host command
0xF170_0054 R/W The fourth argument of the host command
0xF170_0058 R
0xF170_0064 R
0xF170_0068 R
0xF170_0080 R
0xF170_0508 R/W DRAM base address which indicates the
Description
bit has following interpretation.
0 = Reset
1 = Release
An interrupt is raised when MFC enables
the INTERRUPT bit. Host CPU needs to
check this register, properly process an ISR
(Interrupt Service Routine), and clear the
INTERRUPT bit.
Host can send command to MFC to open
instance or close instance.
MFC can respond to host using the
MFC_RISC2HOST_COMMAND register
This register is used with the
MFC_RISC2HOST_COMMAND register
Firmware version information register
Debug information output register 1
Debug information output register 2
Firmware status register
base address for the memory map of the
port A
6 5BMULTI FORMAT CODEC
Reset Value
0x000003fe
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0xD3000000
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