Samsung S5PC110 Manual page 1730

S5PC110_UM
10.3.6.62 Rx Related Register (CEC_ RX_STATUS_3, R, Address = 0xE1B0_00E4)
CEC_RX_STATUS_3
-
Sampling_Error
Low_Time_Error
Start_Bit_Error
-
CEC_Line_Error
Bit
[7] Reserved
[6] Specifies the CEC Rx sampling error flag bit.
0 = No sampling error occurs
1 = A sampling error occurs while receiving a message
CEC Rx samples the CEC bus three times (at 1.00, 1.05,
and 1.10 ms) and sets this bit if Check_Sampling_Error
bit in CEC_RX_CTRL_0 is set and if three samples are
not identical.
It will be cleared if Clear_Intr_Rx_Done or
Clear_Intr_Rx_Error bit in CEC_INTR_CLEAR register is
set to 0.
[5] Specifies the CEC Rx low-time error flag bit.
0 = No low-time error occurs
1 = A low-time error occurs while receiving a message
While receiving each bit from the CEC bus, CEC Rx
checks the duration of logical 0 from the start of one-bit
transfer (falling edge on the CEC bus). If the duration is
longer than the maximum time, the CEC bus can be
logical 0 (maximum 1.7 ms). CEC RX sets this bit.
This bit field will be set to 0 if Clear_Intr_Rx_Done or
Clear_Intr_Rx_Error bit in CEC_INTR_CLEAR register is
set.
[4] Specifies the CEC Rx start bit error flag bit.
0 = No start bit error occurs
1 = A start bit error occurs while receiving a message
While receiving a start bit from the CEC bus, CEC Rx
checks the duration of logical 0 and 1 of a starting bit (as
specified in CEC spec. page CEC-8). If the duration does
not meet the spec., CEC RX sets this bit.
This bit field will be set to 0 if Clear_Intr_Rx_Done or
Clear_Intr_Rx_Error bit in CEC_INTR_CLEAR register is
set.
[3:1] Reserved
[0] Specifies the CEC Rx line error flag bit.
0 = No line error occurs
1 = A start bit error line occurs while receiving a message
In CEC spec. page CEC-13, CEC line error occurs in a
period when two consecutive falling edges is smaller than
a minimum data bit period. Rx checks for this condition,
and if it occurs, it sends the line error notification, that is,
sends logical 0 for more than 1.4~1.6 times of the
nominal data bit period (2.4ms).
This bit will be cleared:
- if Rx_Enable bit of CEC_RX_CTRL_0 is set
- if Clear_Intr_Rx_Done or Clear_Intr_Rx_Error bit in
10 9BHIGH-DEFINITION MULTIMEDIA INTERFACE
Description Initial State
0
0
0
0
3b000
0
10-121