Interrupt Sources; Interrupt Priority Level Bits; External Interrupt; Central Processor Interrupt Priorities Within An Ipl - Motorola DSP56000 Manual

24-bit digital signal processor

Hide thumbs Also See for DSP56000:

Table of Contents

EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING)

Table 7-3 Interrupt Priority Level Bits

with the same IPL are pending, a second fixed-priority structure within that IPL deter-

mines which interrupt the processor will service. The fixed priority of interrupts within an

IPL and the interrupt enable bits for all interrupts are shown in Table 7-5.

7.3.3 Interrupt Sources

Interrupts can originate from any of the vector addresses listed in Table 7-6, which

shows the corresponding interrupt starting address for each interrupt source. These

addresses are located in the first 64 locations of program memory.

Table 7-5 Central Processor Interrupt Priorities Within an IPL

Level 3 (Nonmaskable)

Hardware RESET

Levels 0, 1, 2 (Maskable)

IRQA (External Interrupt)

IRQB (External Interrupt)

PROCESSING STATES

Table 7-4 External Interrupt

IRQA Mode Bits

IRQB Mode Bits

Table of Contents