A.9 Instruction Sequence Restrictions; A-14 Memory Access Timing Summary - Motorola DSP56000 Manual

24-bit digital signal processor

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Table A-14 Memory Access Timing Summary

Note 1: wx = external X memory access wait states

wy = external Y memory access wait states

wp = external P memory access wait states

wio = external I/O memory access wait states

Note 2: wx, wy, wp, and wio are programmable from 0 - 15 wait states in the port A bus control register (BCR).

INSTRUCTION SEQUENCE RESTRICTIONS

Due to the pipelined nature of the DSP56K central processor, there are certain instruc-

tion sequences that are forbidden and will cause undefined operation. Most of these

restricted sequences would cause contention for an internal resource, such as the stack

Most of the following restrictions represent very unusual operations which probably

would never be used but are listed only for completeness.

Note: The DSP56K macro assembler is designed to recognize all restrictions and flag

them as errors at the source code level. Since many of these are instruction sequence

restrictions, they cannot be flagged as errors at the object code level such as when using

the DSP56K simulator's single-line assembler. Therefore, if any changes are made at

the object code level using the simulator, the user should always re-assemble his pro-

gram at the source code level using the DSP56K macro assembler to verify that no

restricted instruction sequences have been generated.

INSTRUCTION SEQUENCE RESTRICTIONS

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