Table 3-3 Operating Modes - Motorola DSP56009 User Manual

• Mode 1—In this mode, the bootstrap ROM is enabled and the bootstrap
program is executed after hardware reset. The internal Program RAM is
loaded with up to 512 words from an external byte-wide static memory
connected to the External Memory Interface (EMI). The EMI operates in the
SRAM Absolute Addressing mode with the slowest SRAM timing. It is
assumed that the chip select control for the external memory is the GPIO3 pin.
• Mode 2—In this mode, the bootstrap ROM is enabled and the bootstrap
program is executed after hardware reset. The bootstrap program ends up in
the first location of the Program ROM (program address $2000).
• Mode 3—Reserved—It is not possible to reach this operating mode during
hardware reset. If an attempt is made, the chip will default to mode 1.
• Mode 4—Reserved
• Mode 5—In this mode, the bootstrap ROM is enabled and the bootstrap
program is executed after hardware reset. The internal Program RAM is
loaded with up to 512 words from the Serial Host Interface (SHI). The SHI
operates in the SPI Slave mode, with 24-bit word width. Mode 5 bootstrap
terminates by setting the operating mode to 0 and jumping to the reset vector
at address $0000.
• Mode 6—Reserved
• Mode 7—In this mode, the bootstrap ROM is enabled and the bootstrap
program is executed after hardware reset. The internal Program RAM is
loaded with up to 512 words from the Serial Host Interface (SHI). The SHI
operates in the I
terminates by setting the operating mode to 0 and jumping to the reset vector
at address $0000.
MMM
Mode
C B A
0
1
2
3
4
5
6
7
MOTOROLA
2
C Slave mode, with 24-bit word width. Mode 7 bootstrap

Table 3-3 Operating Modes

000 Normal operation, bootstrap disabled
001 Bootstrap from EMI
010 Wake up in Program ROM address $2000
011 Reserved
100 Reserved
101 Bootstrap from SHI (SPI mode)
110 Reserved
111
Bootstrap from SHI (I
DSP56009 User's Manual
Memory, Operating Modes, and Interrupts
Operating Mode
2
C mode)
Operating Modes
3-13