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word is optional, it is so indicated. The values which can be assumed by each of the
variables in the various instruction fields are shown under the instruction field's
heading. Note that the symbols used in decoding the various opcode fields of an
instruction are completely arbitrary . Furthermore, the opcode symbols used in
one instruction are completely independent of the opcode symbols used in a dif-
ferent instruction.
7. Timing: The number of oscillator clock cycles required for each instruction syntax is
given. This information provides the user a basis for comparison of the execution
times of the various instructions in oscillator clock cycles. Refer to Table A-1 and
A.7 INSTRUCTION TIMING for a complete explanation of instruction timing, includ-
ing the meaning of the symbols ''aio'', ''ap'', ''ax'', ''ay'', ''axy'', ''ea'', ''jx'', ''mv'',
''mvb'', ''mvc'', ''mvm'', ''mvp'', ''rx'', ''wio'', ''wp'', ''wx'', and ''wy''.
8. Memory: The number of program memory words required for each instruction syn-
tax is given. This information provides the user a basis for comparison of the num-
ber of program memory locations required for each of the various instructions in 24-
bit program memory words. Refer to Table A-1 and A.7 INSTRUCTION TIMING for
a complete explanation of instruction memory requirements, including the meaning
of the symbols ''ea'' and ''mv''.
A.2
NOTATION
Each instruction description contains symbols used to abbreviate certain operands and
operations. Table A-1 lists the symbols used and their respective meanings. Depending
on the context, registers refer to either the register itself or the contents of the register.
A.3
ADDRESSING MODES
The addressing modes are grouped into three categories: register direct, address regis-
ter indirect, and special. These addressing modes are summarized in Table A-2. All
address calculations are performed in the address ALU to minimize execution time and
loop overhead. Addressing modes, which specify whether the operands are in registers,
in memory, or in the instruction itself (such as immediate data), provide the specific
address of the operands.
The register direct addressing mode can be subclassified according to the specific regis-
ter addressed. The data registers include X1, X0, Y1, Y0, X, Y, A2, A1, A0, B2, B1, B0,
A, and B. The control registers include SR, OMR, SP, SSH, SSL, LA, LC, CCR, and MR.
Address register indirect modes use an address register Rn (R0–R7) to point to locations
in X, Y, and P memory. The contents of the Rn address register (Rn) is the effective
address (ea) of the specified operand, except in the ''indexed by offset'' mode where the
effective address (ea) is (Rn+Nn). Address register indirect modes use an address mod-
ifier register Mn to specify the type of arithmetic to be used to update the address regis-
ter Rn. If an addressing mode specifies an address offset register Nn, the given address
offset register is used to update the corresponding address register Rn. The Rn address
register may only use the corresponding address offset register Nn and the correspond-
ing address modifier register Mn. For example, the address register R0 may only use the
A - 2
Freescale Semiconductor, Inc.
DSP56000/DSP56001 USER'S MANUAL
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
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