Icr Reserved-Bit 2; Icr Hi Flag 0 (Hf0)-Bit 3; Table 4-2 Horeq Pin Definition - Motorola DSP56012 User Manual

In DMA modes, TREQ must be set or cleared by software to select the direction of
DMA transfers. Setting TREQ sets the direction of DMA transfer to be host to DSP
and enables the HOREQ pin to request data transfer.
Note: Hardware reset, software reset, individual reset, and Stop mode clear TREQ.
Table 4-2 summarizes the effect of RREQ and TREQ on the HOREQ pin.
TREQ
4.4.5.3.3 ICR Reserved—Bit 2
This bit is reserved and unused, reads as 0 and should be written with 0 for
compatibility with future device revisions.
4.4.5.3.4 ICR HI Flag 0 (HF0)—Bit 3
The HI Flag 0 (HF0) bit is used as a general purpose flag for host-to-DSP
communication. HF0 can be set or cleared by the host processor and cannot be
changed by the DSP. HF0 is visible to the DSP as the read-only flag HF0 in the HSR
(see Figure 4-9 on page 4-18).
Note: Hardware reset, software reset, individual reset, and Stop mode clear HF0.
MOTOROLA

Table 4-2 HOREQ Pin Definition

RREQ
Interrupt Mode
0 0
0 1
1 0
1 1
DMA Mode
0 0
0 1
1 0
1 1
DSP56012 User's Manual
HOREQ Pin
No Interrupts (Polling)
RXDF Request (Interrupt)
TXDE Request (Interrupt)
RXDF and TXDE Request
(Interrupts)
No DMA
DSP to Host Request (RX)
Host to DSP Request (TX)
Undefined (Illegal)
Parallel Host Interface
Host Interface (HI)
4-25