Table 7-4 Mode And Signal Definition Table - Motorola DSP56309 User Manual

Enhanced Synchronous Serial Interface (ESSI)
ESSI Programming Model
The TE1 bit is cleared by either a hardware RESET signal or a software RESET
instruction.
Note: The setting of the TE1 bit does not affect the generation of frame sync or
output flags.
7.4.2.16 CRB ESSI Transmit 0 Enable (TE0) Bit 16
The TE0 bit enables the transfer of data from TX0 to transmit shift register 0. TE0 is
functional when the ESSI is in either synchronous or asynchronous mode.
When TE0 is set and a frame sync is detected, the transmitter 0 is enabled for that frame.
When TE0 is cleared, transmitter 0 is disabled after completing transmission of data
currently in the ESSI transmit shift register. The STD output is tri-stated, and any data
present in TX0 is not transmitted (i.e., data can be written to TX0 with TE0 cleared; the
TDE bit is cleared, but data is not transferred to the transmit shift register 0).
The TE0 bit is cleared by either a hardware RESET signal or a software RESET
instruction.
The transmit enable sequence for on-demand mode can be the same as for normal mode,
or TE0 can be left enabled.
Note: Transmitter 0 is the only transmitter that can operate in asynchronous mode
(SYN = 0). TE0 does not affect the generation of frame sync or output flags.
Table 7-4 summarizes the preceding sections; it shows possible settings of control bits
and their associated signals.
Control Bits
SYN TE0 TE1
0 0 X
0 0 X
0 1 X
0 1 X
1 0 0
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Table 7-4 Mode and Signal Definition Table

TE2 RE SC0
X 0 U
X 1 RXC
X 0 U
X 1 RXC
0 0 U
DSP56309UM/D
ESSI Signals
SC1 SC2 SCK
U U U
FSR U U
U FST TXC
FSR FST TXC
U U U
STD SRD
U U
U RD
TD0 U
TD0 RD
U U
MOTOROLA