Chip Operating Modes; Bootstrap Mode (Mode 0) - Motorola DSP56156 Manual

Operating Mode Summary — Program RAM Part
3.1.1.4

Chip Operating Modes

The DSP operating modes determine the memory maps for program and data memories
and the startup procedure when the DSP leaves the reset state. The MODA, MODB, and
MODC pins are sampled as the DSP leaves the reset state, and the initial operating mode
of the DSP is set accordingly. After the reset state is exited, the MODA and MODB pins
become general-purpose interrupt pins, IRQA, and IRQB. One of three initial operating
modes is selected: single chip, normal expanded, or development. Chip operating modes
can be changed by writing the operating mode bits (MB, MA) in the OMR. Changing op-
erating modes does not reset the DSP. It is desirable to disable interrupts immediately
before changing the OMR to prevent an interrupt from going to the wrong memory loca-
tion. Also, one no-operation (NOP) instruction should be included after changing the OMR
to allow for remapping to occur.
3.1.1.4.1

Bootstrap Mode (Mode 0)

Mode 0 is one of two bootstrap modes which have all internal program and data RAM
memories enabled (see Figure 3-1). This mode can be entered by either grounding both
mode pins and resetting the chip or by writing to the OMR and changing the MA and MB
bits. When the operating mode is first changed to Mode 0, the DSP56156 executes a boot-
strap program which loads program memory from a byte wide memory located at
P:$C000 (see Table 3-1). Section 3.1.2.2 describes the bootstrap operation. The memory
maps for Mode 0 and Mode 1 are identical. The difference between Mode 0 and Mode 2
is the location of the reset vector in program memory. The reset vector location in Mode 0
is at internal memory location P:$0000. The reset vector location in Mode 2 is at external
memory location P:$E000.
MOTOROLA OPERATING MODES AND MEMORY SPACES
RAM MEMORY DESCRIPTION
Table 3-1
Operating M M
Mode B A
Special 0 0 Bootstrap from an external
Bootstrap 1 byte-wide memory located
at P:$C000.
Internal reset at P:$0000
Special 0 1 Bootstrap from the Host port
Bootstrap 2 (P:$C000 bit 15=0) or SSI0
(P:$C000 bit 15=0).
External reset at P:$0000
Normal 1 0 Internal PRAM enabled.
Expanded External reset at P:$E000
Development 1 1 Internal program memory
Expanded disabled.
External reset at P:$0000.
Description
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