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Operating Modes
9.3.2
Signal Measurement Modes
The following signal measurement and pulse width modulation modes are provided:
n
Measurement input width (Mode 4)
n
Measurement input period (Mode 5)
n
Measurement capture (Mode 6)
n
Pulse width modulation (PWM) mode (Mode 7)
The external signal synchronizes with the internal clock that increments the counter. This
synchronization process can cause the number of clocks measured for the selected signal
value to vary from the actual signal value by plus or minus one counter clock cycle.
9.3.2.1 Measurement Input Width (Mode 4)
Bit Settings
TC3
TC2
TC1
0
1
0
In Mode 4, the timer counts the number of clocks that occur between opposite edges of an
input signal. After the first appropriate transition (as determined by the TCSR[INV] bit)
occurs on the
input signal, the counter is loaded with the TLR value. If TCSR[INV] is set,
TIO
the timer starts on the first high-to-low (1 to 0) signal transition on the
bit is cleared, the timer starts on the first low-to-high (that is, 0 to 1) transition on the
signal. When the first transition opposite in polarity to the INV bit setting occurs on the
signal, the counter stops. TCSR[TCF] is set and a compare interrupt is generated if the
TCSR[TCIE] bit is set. The value of the counter (which measures the width of the TIO pulse)
is loaded into the TCR, which can be read to determine the external signal pulse width. If the
TCSR[TRM] bit is set, the counter is loaded with the TLR value on the first timer clock
received following the next valid transition on the
TCSR[TRM] is cleared, the counter continues to increment on each timer clock. This process
repeats until the timer is disabled.
9-14
TC0
Mode
0
4
Input width
DSP56303 User's Manual
Mode Characteristics
Name
Function
Measurement
input signal, and the count resumes. If
TIO
TIO
Clock
Input
Internal
signal. If the INV
TIO
TIO
TIO
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