Table 10-10 Breakpoint 1 Condition Select Table; Table 10-11 Breakpoint 0 And 1 Event Select Table - Motorola DSP56309 User Manual

On-Chip Emulation Module
OnCE Memory Breakpoint Logic
10.5.6.5 Breakpoint 1 Condition Code Select (CC10ÐCC11)
Bits 8Ð9
The CC10ÐCC11 bits define the condition of the comparison between the current
memory address (OMAL0) and the OnCE Memory Limit Register 1 (OMLR1). See
Table 10-10 for the definition of the CC10ÐCC11 bits.

Table 10-10 Breakpoint 1 Condition Select Table

CC11 CC10
0 0
0 1
1 0
1 1
10.5.6.6 Breakpoint 0 and 1 Event Select (BT0ÐBT1)
Bits 10Ð11
The BT0ÐBT1 bits define the sequence between breakpoint 0 and 1. If the condition
defined by BT0ÐBT1 is met, then the OnCE Breakpoint Counter (OMBC) is decremented.
See Table 10-11 for the definition of the BT0ÐBT1 bits.

Table 10-11 Breakpoint 0 and 1 Event Select Table

BT1
0
0
1
1
10.5.6.7 OnCE Memory Breakpoint Counter (OMBC)
The OMBC is a 16-bit counter that is loaded with a value equal to the number of times
minus one that a memory access event should occur before a memory breakpoint is
declared. The memory access event is specified by the OBCR and by the memory limit
registers. On each occurrence of the memory access event, the breakpoint counter is
decremented. When the counter reaches 0 and a new occurrence takes place, the chip
enters debug mode. The OMBC can be read or written through the JTAG port. Every
time that the limit register is changed or a different breakpoint event is selected in the
OBCR, the breakpoint counter must be written afterwards. This insures that the OnCE
10-14
Breakpoint on not equal
Breakpoint on equal
Breakpoint on less than
Breakpoint on greater than
BT0
0 Breakpoint 0 and Breakpoint 1
1 Breakpoint 0 or Breakpoint 1
0 Breakpoint 1 after Breakpoint 0
1 Breakpoint 0 after Breakpoint 1
DSP56309UM/D
Description
Description
MOTOROLA