Pll Pins; Pctl Chip Clock Source Bit (Csrc) - Bit 21; Pctl Reserved Bit - Bit 23; Section 9.3 Pll Pins - Motorola DSP56000 Manual

Table 9-4 Clock Output Disable Bits COD0-COD1
COD1
0
0
1
1

9.2.5.7 PCTL Chip Clock Source Bit (CSRC) - Bit 21

The CSRC bit specifies whether the clock for the chip is taken from the output of the VCO
or is taken from the output of the Low Power Divider (LPD). When CSRC is set, the clock
for the chip is taken from the VCO. When CSRC is cleared, the clock for the chip is taken
from the output of the LPD. See Section 9.4.8 for restrictions. CSRC is cleared by hard-
ware reset.
9.2.5.8 PCTL CKOUT Clock Source Bit (CKOS) - Bit 22
The CKOS bit specifies whether the CKOUT clock output is taken from the output of the
VCO or is taken from the output of the Low Power Divider (LPD). When CKOS is set, the
CKOUT clock output is taken from the VCO. When CKOS is cleared, the CKOUT clock
output is taken from the output of the LPD. If the PLL is disabled (PEN=0), CKOUT is tak-
en from EXTAL. See Section 9.4.8 for restrictions. CKOS is cleared by hardware reset.

9.2.5.9 PCTL Reserved Bit - Bit 23

This bit is reserved for future expansion. It reads as zero and should be written with zero
for future compatibility.
9.3

PLL PINS

Some of the PLL pins need not be implemented. The specific PLL pin configuration for
each DSP56K chip implementation is available in the respective device's user's manual.
The following pins are dedicated to the PLL operation:
PVCC VCC dedicated to the analog PLL circuits. The voltage should be well regulated
and the pin should be provided with an extremely low impedance path to the
VCC power rail. PVCC should be bypassed to PGND by a 0.1
located as close as possible to the chip package.
PGND GND dedicated to the analog PLL circuits. The pin should be provided with an
extremely low impedance path to ground. PVCC should be bypassed to PGND
µ
by a 0.1 F capacitor located as close as possible to the chip package.
MOTOROLA
PLL PINS
COD0
0 Clock Out Enabled, Full Strength Output Buffer
1 Clock Out Enabled, 2/3 Strength Output Buffer
0 Clock Out Enabled, 1/3 Strength Output Buffer
1 Clock Out Disabled
PLL CLOCK OSCILLATOR
CKOUT Pin
µ
F capacitor
9 - 9