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Serial Audio Interface
Serial Audio Interface Programming Model
discarded according to the Receiver Data Word Truncation (RDWT) control bit (see
below). RWL[1:0] are also used to generate the word select indication when the
receiver section is configured as master (RMST = 1). The RWL[1:0] bits are cleared
during hardware reset and software reset.
6.3.2.6
RCS Receiver Data Shift Direction (RDIR)—Bit 6
The read/write Receiver data shift Direction (RDIR) control bit selects the shift
direction of the received data. When RDIR is cleared, receive data is shifted in most
significant bit first. When RDIR is set, the data is shifted in least significant bit first
(see Figure 6-5 ). The RDIR bit is cleared during hardware reset and software reset.
SCKR
MSB
RDIR = 0
SDI
LSB
RDIR = 1
SDI
Figure 6-5 Receiver Data Shift Direction (RDIR) Programming
6.3.2.7
RCS Receiver Left Right Selection (RLRS)—Bit 7
The read/write Receiver Left Right Selection (RLRS) control bit selects the polarity of
the Receiver Word Select (WSR) signal that identifies the Left or Right word in the
input bit stream. When RLRS is cleared, WSR low identifies the Left data word and
WSR high identifies the Right data word. When RLRS is set, WSR high identifies the
Left data word and WSR low identifies the Right data word (see Figure 6-6 ). The
RLRS bit is cleared during hardware reset and software reset.
RLRS = 0
WSR
WSR
RLRS = 1
Figure 6-6 Receiver Left/Right Selection (RLRS) Programming
6-12
1
2
3
4
5
Left
Left
DSP56009 User's Manual
6
7
8
9
10
11
12
13
14
15
LSB
MSB
AA0431
Right
Right
AA0432
MOTOROLA
16
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